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4.3
Acceleration Data Transfers
Acceleration data requests are initiated when the Acceleration bit of the SPI command message (A) is set to a logic ’1’. The
Axis Selection bit (AX) and the Offset Cancellation Selection bit (OC) of the command message select the type of acceleration
data requested, as shown in Table 31 .
Table 31. Acceleration Data Request
Acceleration Data Request Command Information
Data Type
Axis Selection Bit (AX)
Offset Cancellation Select (OC)
0
0
1
1
0
1
0
1
X-Axis Offset Cancelled Data
X-Axis Raw Data
Y-Axis Offset Cancelled Data
Y-Axis Raw Data
To verify that MMA68xx is configured as expected, each acceleration data request includes the configuration information that
impacts the output data. The requested configuration is compared against the data programmed in the writable register array.
Details are shown in Table 32 .
Table 32. Acceleration Data Request Configuration Information
Programmable Option
Signed or Unsigned Data
Arming Function or PCM Output
Command Message Bit
SD
ARM
Writable Register Information
DEVCFG[4] (SD)
DEVCFG[2] || DEVCFG[1] (A_CFG[2] || A_CFG[1])
If the data listed in Table 32 does not does not match, an Acceleration Data Request Mismatch failure is detected and no ac-
celeration data is transmitted. Reference Section 4.5.3.1 .
Acceleration data request commands include a parity bit (P). Odd parity is employed. The number of logic ’1’ bits in the accel-
eration data request command must be an odd number.
Acceleration data is transmitted on the next SPI message if and only if all of the following conditions are met:
? The DEVINIT bit in the DEVSTAT register is not set
? The DEVRES bit in the DEVSTAT register is not set
? The IDE bit in the DEVSTAT register is not set (Reference Section 4.5.5 )
? No SPI Error is detected (Reference Section 4.5.1 )
? No MISO Error is detected (Reference Section 4.5.2 )
? No Acceleration Data Request Mismatch failure is detected (Reference Section 4.5.3.1 )
? No Self-Test Error is present (reference Section 4.5.5.2 )
If the above conditions are met, MMA68xx responds with a “valid acceleration data request” response as shown in Table 30 .
Otherwise, MMA68xx responds as specified in Section 4.5 .
4.4
Register Access Operations
Two types of register access operations are supported; register write, and register read. Register access operations are initi-
ated when the acceleration bit (A) of the command message is set to a logic ’0’. The operation to be performed is indicated by
the Access Selection bit (AX) of the command message.
Access Selection Bit (AX)
0
1
Operation
Register Read
Register Write
Register Access operations include a parity bit (P). Odd parity is employed. The number of logic ’1’ bits in the Register Access
operation must be an odd number.
MMA68xx
Sensors
Freescale Semiconductor, Inc.
47
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